Sample behavioral waveforms for design file PLL1.vhd

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design PLL1.vhd. The design PLL1.vhd has Stratix AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps.

Fig. 1 : Wave showing NORMAL mode operation.