This Board Update Portal web page is being served by a design running in the FPGA on your development board. This page, in coordination with the FPGA design serving it, allows you to write new FPGA images to the flash on your board and provides links to useful information on the Altera^® website. The FPGA design contains a Nios^® II CPU and the Triple Speed Ethernet MAC MegaCore^® function. When you install the development kit design files on your system, the design files for the Board Update Portal FPGA design are installed in the
.../kits/arriaIIGX_2agx125_fpga/examples/board_update_portal directory. This design is one example of how to remotely update an FPGA system over Ethernet. Remote Update can be accomplished without a web server, and it can also be used to update just the firmware of an embedded FPGA system. Please see application note AN429 to learn more about Remote Update.

Instructions on preparing your own .sof/.elf files for uploading to flash via the Board Update Portal are available here.