---

clk_50

clock_source v13.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

timer

altera_avalon_timer v13.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 1 periodUnits MSEC resetOutput false snapshot true timeoutPulseOutput false systemFrequency 10000000 timerPreset FULL_FEATURED periodUnitsString ms valueInSecond 0 loadValue 9999 mult 0 ticksPerSec 1000 slave_address_width 3 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 COUNTER_SIZE 32 FIXED_PERIOD 0 FREQ 10000000 LOAD_VALUE 9999 MULT 0.001 PERIOD 1 PERIOD_UNITS ms RESET_OUTPUT 0 SNAPSHOT 1 TICKS_PER_SEC 1000.0 TIMEOUT_PULSE_OUTPUT 0

---

onchip_memory2

altera_avalon_onchip_memory2 v13.1

Parameters allowInSystemMemoryContentEditor false blockType AUTO dataWidth 32 dualPort false initMemContent true initializationFileName onchip_memory2 instanceID NONE memorySize 160000 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false simMemInitOnlyFilename 0 singleClockOperation false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false useShallowMemBlocks false writable true ecc_enabled false autoInitializationFileName DE1_SoC_QSYS_onchip_memory2 deviceFamily CYCLONEV deviceFeatures ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 derived_set_addr_width 16 derived_set_data_width 32 derived_gui_ram_block_type Automatic derived_is_hardcopy false derived_init_file_name DE1_SoC_QSYS_onchip_memory2.hex generateLegacySim false

  

Software Assignments ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 CONTENTS_INFO "" DUAL_PORT 0 GUI_RAM_BLOCK_TYPE AUTO INIT_CONTENTS_FILE DE1_SoC_QSYS_onchip_memory2 INIT_MEM_CONTENT 1 INSTANCE_ID NONE NON_DEFAULT_INIT_FILE_ENABLED 0 RAM_BLOCK_TYPE AUTO READ_DURING_WRITE_MODE DONT_CARE SINGLE_CLOCK_OP 0 SIZE_MULTIPLE 1 SIZE_VALUE 160000 WRITABLE 1

---

sdram

altera_avalon_new_sdram_controller v13.1

Parameters TAC 5.5 TRCD 20.0 TRFC 70.0 TRP 20.0 TWR 14.0 casLatency 3 columnWidth 10 dataWidth 16 generateSimulationModel true initRefreshCommands 2 model custom numberOfBanks 4 numberOfChipSelects 1 pinsSharedViaTriState false powerUpDelay 100.0 refreshPeriod 15.625 rowWidth 13 masteredTristateBridgeSlave 0 TMRD 3 initNOPDelay 0.0 registerDataIn true clockRate 130000000 componentName DE1_SoC_QSYS_sdram size 67108864 addressWidth 25 bankWidth 2 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CAS_LATENCY 3 CONTENTS_INFO INIT_NOP_DELAY 0.0 INIT_REFRESH_COMMANDS 2 IS_INITIALIZED 1 POWERUP_DELAY 100.0 REFRESH_PERIOD 15.625 REGISTER_DATA_IN 1 SDRAM_ADDR_WIDTH 25 SDRAM_BANK_WIDTH 2 SDRAM_COL_WIDTH 10 SDRAM_DATA_WIDTH 16 SDRAM_NUM_BANKS 4 SDRAM_NUM_CHIPSELECTS 1 SDRAM_ROW_WIDTH 13 SHARED_DATA 0 SIM_MODEL_BASE 1 STARVATION_INDICATOR 0 TRISTATE_BRIDGE_SLAVE "" T_AC 5.5 T_MRD 3 T_RCD 20.0 T_RFC 70.0 T_RP 20.0 T_WR 14.0

---

i2c_scl

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 10000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 10000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

i2c_sda

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 10000000 derived_has_tri true derived_has_out false derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 10000000 HAS_IN 0 HAS_OUT 0 HAS_TRI 1 IRQ_TYPE NONE RESET_VALUE 0

---

jtag_uart

altera_avalon_jtag_uart v13.1

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 avalonSpec 2.0 legacySignalAllow false enableInteractiveInput false enableInteractiveOutput true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments READ_DEPTH 64 READ_THRESHOLD 8 WRITE_DEPTH 64 WRITE_THRESHOLD 8

---

alt_vip_cti_0

alt_vip_cti v13.1

Parameters FAMILY CYCLONEV BPS 8 NUMBER_OF_COLOUR_PLANES 2 COLOUR_PLANES_ARE_IN_PARALLEL 0 SYNC_TO 0 USE_EMBEDDED_SYNCS 1 ADD_DATA_ENABLE_SIGNAL 0 ACCEPT_COLOURS_IN_SEQ 0 USE_STD 0 STD_WIDTH 1 GENERATE_ANC 0 INTERLACED 1 H_ACTIVE_PIXELS_F0 720 V_ACTIVE_LINES_F0 288 V_ACTIVE_LINES_F1 288 FIFO_DEPTH 1440 CLOCKS_ARE_SAME 0 USE_CONTROL 1 GENERATE_SYNC 0 AUTO_IS_CLK_RST_CLOCK_RATE 130000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

alt_vip_cpr_0

alt_vip_cpr v13.1

Parameters AUTO_DEVICE_FAMILY CYCLONEV DIN1_ENABLED 0 DOUT1_SYMBOLS_PER_BEAT 0 DOUT0_SYMBOLS_PER_BEAT 2 DOUT1_ENABLED 0 PARAMETERISATION <colourPatternRearrangerParams><CPR_NAME>Color Plane Sequencer</CPR_NAME><CPR_BPS>8</CPR_BPS><CPR_PORTS><INPUT_PORT><NAME>din0</NAME><STREAMING_DESCRIPTOR>[C,Y]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED></INPUT_PORT><INPUT_PORT><NAME>din1</NAME><STREAMING_DESCRIPTOR>[Channel]</STREAMING_DESCRIPTOR><ENABLED>false</ENABLED></INPUT_PORT><OUTPUT_PORT><NAME>dout0</NAME><STREAMING_DESCRIPTOR>[C:Y]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT><OUTPUT_PORT><NAME>dout1</NAME><STREAMING_DESCRIPTOR>[Channel]</STREAMING_DESCRIPTOR><ENABLED>false</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT></CPR_PORTS><CPR_INPUT_2_PIXELS>false</CPR_INPUT_2_PIXELS></colourPatternRearrangerParams> DIN0_SYMBOLS_PER_BEAT 1 DIN1_SYMBOLS_PER_BEAT 0 deviceFamily Cyclone V generateLegacySim false

  

Software Assignments (none)

---

alt_vip_dil_0

alt_vip_dil v13.1

Parameters AUTO_DEVICE_FAMILY CYCLONEV AUTO_WRITE_MASTER_MAX_READ_LATENCY 2 AUTO_MA_CONTROL_CLOCKS_SAME 0 AUTO_MOTION_READ_MASTER_INTERRUPT_USED_MASK -1 AUTO_READ_MASTER_CLOCKS_SAME 0 READ_MASTERS_REQUIRED 0 WRITE_MASTERS_REQUIRED 0 PARAMETERISATION <deinterlacerParams><DIL_NAME>my_deinterlacing_core</DIL_NAME><DIL_MAX_WIDTH>720</DIL_MAX_WIDTH><DIL_MAX_HEIGHT>576</DIL_MAX_HEIGHT><DIL_CHANNELS_IN_SEQ>1</DIL_CHANNELS_IN_SEQ><DIL_CHANNELS_IN_PAR>2</DIL_CHANNELS_IN_PAR><DIL_BPS>8</DIL_BPS><DIL_METHOD>DEINTERLACING_BOB_SCANLINE_INTERPOLATION</DIL_METHOD><DIL_FRAMEBUFFERS_ADDR>00</DIL_FRAMEBUFFERS_ADDR><DIL_PRODUCE_FIELDS>DEINTERLACING_F0</DIL_PRODUCE_FIELDS><DIL_BUFFER_AS_THOUGH>DEINTERLACING_NO_BUFFERING</DIL_BUFFER_AS_THOUGH><DIL_DEFAULT_INITIAL_FIELD>FIELD_F0_FIRST</DIL_DEFAULT_INITIAL_FIELD><DIL_MASTER_PORT_WIDTH>64</DIL_MASTER_PORT_WIDTH><DIL_MEM_MASTERS_USE_SEPARATE_CLOCK>0</DIL_MEM_MASTERS_USE_SEPARATE_CLOCK><DIL_EDGE_DEPENDENT_INTERPOLATION>1</DIL_EDGE_DEPENDENT_INTERPOLATION><DIL_MOTION_BLEED>0</DIL_MOTION_BLEED><DIL_RDATA_FIFO_DEPTH>64</DIL_RDATA_FIFO_DEPTH><DIL_RDATA_BURST_TARGET>32</DIL_RDATA_BURST_TARGET><DIL_WDATA_FIFO_DEPTH>64</DIL_WDATA_FIFO_DEPTH><DIL_WDATA_BURST_TARGET>32</DIL_WDATA_BURST_TARGET><DIL_MAX_NUMBER_PACKETS>1</DIL_MAX_NUMBER_PACKETS><DIL_MAX_SYMBOLS_IN_PACKET>10</DIL_MAX_SYMBOLS_IN_PACKET><DIL_MA_RUNTIME_CTRL>0</DIL_MA_RUNTIME_CTRL><DIL_PROPAGATE_PROGRESSIVE>false</DIL_PROPAGATE_PROGRESSIVE><DIL_CONTROLLED_DROP_REPEAT>0</DIL_CONTROLLED_DROP_REPEAT><DIL_MA_422>0</DIL_MA_422><DIL_BURST_ALIGNMENT>0</DIL_BURST_ALIGNMENT></deinterlacerParams> AUTO_MOTION_WRITE_MASTER_CLOCKS_SAME 0 AUTO_MOTION_READ_MASTER_CLOCKS_SAME 0 AUTO_MOTION_READ_MASTER_MAX_READ_LATENCY 2 AUTO_READ_MASTER_INTERRUPT_USED_MASK -1 AUTO_WRITE_MASTER_INTERRUPT_USED_MASK -1 MOTION_MASTERS_REQUIRED 0 AUTO_MOTION_READ_MASTER_NEED_ADDR_WIDTH 62 AUTO_WRITE_MASTER_CLOCKS_SAME 0 AUTO_READ_MASTER_MAX_READ_LATENCY 2 AUTO_WRITE_MASTER_NEED_ADDR_WIDTH 62 AUTO_READ_MASTER_NEED_ADDR_WIDTH 62 AUTO_KER_WRITER_CONTROL_CLOCKS_SAME 0 AUTO_MOTION_WRITE_MASTER_NEED_ADDR_WIDTH 62 AUTO_MOTION_WRITE_MASTER_MAX_READ_LATENCY 2 AUTO_MOTION_WRITE_MASTER_INTERRUPT_USED_MASK -1 deviceFamily Cyclone V generateLegacySim false

  

Software Assignments (none)

---

alt_vip_crs_0

alt_vip_crs v13.1

Parameters AUTO_DEVICE_FAMILY CYCLONEV OUT_CHANNELS_IN_PAR 3 IN_CHANNELS_IN_PAR 2 PARAMETERISATION <chromaResamplerParams><CRS_NAME>chroma_resampler</CRS_NAME><CRS_BPS>8</CRS_BPS><CRS_WIDTH>720</CRS_WIDTH><CRS_HEIGHT>576</CRS_HEIGHT><CRS_PARALLEL_MODE>true</CRS_PARALLEL_MODE><CRS_RESAMPLING><FORMAT><IN>422</IN><OUT>444</OUT></FORMAT><COSITING><V>true</V><H>true</H></COSITING></CRS_RESAMPLING><CRS_ALGORITHM><V><NAME>INTERPOLATION_1D_NEAREST_NEIGHBOUR</NAME><LUMA_ADAPTIVE>false</LUMA_ADAPTIVE></V><H><NAME>INTERPOLATION_1D_FULL_FILTERING</NAME><LUMA_ADAPTIVE>false</LUMA_ADAPTIVE></H></CRS_ALGORITHM></chromaResamplerParams> deviceFamily Cyclone V generateLegacySim false

  

Software Assignments (none)

---

alt_vip_csc_0

alt_vip_csc v13.1

Parameters AUTO_CONTROL_CLOCKS_SAME 0 AUTO_DEVICE_FAMILY CYCLONEV PARAMETERISATION <cscParams> <CSC_NAME>a_csc</CSC_NAME> <CSC_CHANNELS_IN_SEQ>1</CSC_CHANNELS_IN_SEQ> <CSC_CHANNELS_IN_PAR>3</CSC_CHANNELS_IN_PAR> <CSC_INPUT_OUTPUT_DATATYPES> <IODT_INPUT_BPS>8</IODT_INPUT_BPS> <IODT_OUTPUT_BPS>8</IODT_OUTPUT_BPS> <IODT_INPUT_DATA_TYPE>DATA_TYPE_UNSIGNED</IODT_INPUT_DATA_TYPE> <IODT_OUTPUT_DATA_TYPE>DATA_TYPE_UNSIGNED</IODT_OUTPUT_DATA_TYPE> <IODT_USE_INPUT_GUARD_BANDS>true</IODT_USE_INPUT_GUARD_BANDS> <IODT_INPUT_GUARD_MIN>16</IODT_INPUT_GUARD_MIN> <IODT_INPUT_GUARD_MAX>240</IODT_INPUT_GUARD_MAX> <IODT_USE_OUTPUT_GUARD_BANDS>false</IODT_USE_OUTPUT_GUARD_BANDS> <IODT_OUTPUT_GUARD_MIN>0</IODT_OUTPUT_GUARD_MIN> <IODT_OUTPUT_GUARD_MAX>255</IODT_OUTPUT_GUARD_MAX> </CSC_INPUT_OUTPUT_DATATYPES> <CSC_PREDEFINED_CONVERSION>SDTV_YCBCR_TO_CRGB</CSC_PREDEFINED_CONVERSION> <CSC_COEFFICIENTS><row><mult>2.018</mult><mult>0.0</mult><mult>1.164</mult><add>-276.928</add></row><row><mult>-0.391</mult><mult>-0.813</mult><mult>1.164</mult><add>135.488</add></row><row><mult>0.0</mult><mult>1.596</mult><mult>1.164</mult><add>-222.912</add></row></CSC_COEFFICIENTS> <CSC_COEFF_PRECISION> <CPC_INTEGER_BITS>2</CPC_INTEGER_BITS> <CPC_FRACTION_BITS>8</CPC_FRACTION_BITS> <CPC_COEFFS_SIGNED>true</CPC_COEFFS_SIGNED> </CSC_COEFF_PRECISION> <CSC_SUMM_PRECISION> <CPC_INTEGER_BITS>9</CPC_INTEGER_BITS> <CPC_FRACTION_BITS>8</CPC_FRACTION_BITS> <CPC_COEFFS_SIGNED>true</CPC_COEFFS_SIGNED> </CSC_SUMM_PRECISION> <CSC_OUTPUT_CONVERSION> <ODTC_SCALE>0</ODTC_SCALE> <ODTC_FIXEDPOINT_TO_INTEGER>FRACTION_BITS_ROUND_HALF_UP</ODTC_FIXEDPOINT_TO_INTEGER> <ODTC_CONVERT_SIGNED_TO_UNSIGNED>CONVERT_TO_UNSIGNED_SATURATE</ODTC_CONVERT_SIGNED_TO_UNSIGNED> </CSC_OUTPUT_CONVERSION> <CSC_RUNTIME_COEFFICIENTS>false</CSC_RUNTIME_COEFFICIENTS> </cscParams> deviceFamily Cyclone V generateLegacySim false

  

Software Assignments (none)

---

alt_vip_clip_0

alt_vip_clip v13.1

Parameters AUTO_CONTROL_CLOCKS_SAME 0 AUTO_DEVICE_FAMILY CYCLONEV PARAMETERISATION <clipperParams><CLIP_NAME>clipper</CLIP_NAME><CLIP_BPS>8</CLIP_BPS><CLIP_CHANNELS_IN_SEQ>1</CLIP_CHANNELS_IN_SEQ><CLIP_CHANNELS_IN_PAR>3</CLIP_CHANNELS_IN_PAR><CLIP_WIDTH>720</CLIP_WIDTH><CLIP_HEIGHT>576</CLIP_HEIGHT><CLIP_RUNTIME_CONTROL>false</CLIP_RUNTIME_CONTROL><CLIP_OFFSETS_NOT_RECTANGLE>false</CLIP_OFFSETS_NOT_RECTANGLE><CLIP_LEFT_OFFSET>40</CLIP_LEFT_OFFSET><CLIP_RIGHT_OFFSET>640</CLIP_RIGHT_OFFSET><CLIP_TOP_OFFSET>24</CLIP_TOP_OFFSET><CLIP_BOTTOM_OFFSET>480</CLIP_BOTTOM_OFFSET></clipperParams> deviceFamily Cyclone V generateLegacySim false

  

Software Assignments (none)

---

alt_vip_vfb_0

alt_vip_vfb v13.1

Parameters AUTO_DEVICE_FAMILY CYCLONEV AUTO_READ_MASTER_INTERRUPT_USED_MASK 0 AUTO_WRITE_MASTER_MAX_READ_LATENCY 2 AUTO_WRITE_MASTER_INTERRUPT_USED_MASK 0 AUTO_WRITE_MASTER_CLOCKS_SAME 2 AUTO_READ_MASTER_MAX_READ_LATENCY 2 AUTO_WRITE_MASTER_NEED_ADDR_WIDTH 27 AUTO_READ_MASTER_NEED_ADDR_WIDTH 27 AUTO_WRITER_CONTROL_CLOCKS_SAME 0 AUTO_READ_MASTER_CLOCKS_SAME 2 AUTO_READER_CONTROL_CLOCKS_SAME 0 PARAMETERISATION <frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>270</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>200</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>0</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>1</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>1</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>00000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>32</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>0</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>256</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>4</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>256</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>4</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>1</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>0</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>0</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>0</VFB_DROP_INVALID_FIELDS></frameBufferParams> deviceFamily Cyclone V generateLegacySim false

  

Software Assignments (none)

---

td_status

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Input edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 2 clockRate 10000000 derived_has_tri false derived_has_out false derived_has_in true derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 2 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 10000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

td_reset_n

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 10000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 10000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

clock_crossing_io_slow

altera_avalon_mm_clock_crossing_bridge v13.1

Parameters DATA_WIDTH 32 SYMBOL_WIDTH 8 ADDRESS_WIDTH 9 ADDRESS_UNITS SYMBOLS BURSTCOUNT_WIDTH 1 MAX_BURST_SIZE 1 COMMAND_FIFO_DEPTH 32 RESPONSE_FIFO_DEPTH 256 MASTER_SYNC_DEPTH 3 SLAVE_SYNC_DEPTH 3 AUTO_M0_CLK_CLOCK_RATE 10000000 AUTO_S0_CLK_CLOCK_RATE 130000000 AUTO_DEVICE_FAMILY CYCLONEV deviceFamily Cyclone V generateLegacySim false

  

Software Assignments (none)

---

cpu

altera_nios2_qsys v13.1

Parameters setting_showUnpublishedSettings false setting_showInternalSettings false setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_bit31BypassDCache true setting_bigEndian false setting_export_large_RAMs false setting_asic_enabled false setting_asic_synopsys_translate_on_off false setting_oci_export_jtag_signals false setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTrace_user false setting_activateTestEndChecker false setting_ecc_sim_test_ports false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false setting_breakslaveoveride false muldiv_divider false mpu_useLimit false mpu_enabled false mmu_enabled false mmu_autoAssignTlbPtrSz true manuallyAssignCpuID false debug_triggerArming true debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false dcache_omitDataMaster false cpuReset false is_hardcopy_compatible false setting_shadowRegisterSets 0 mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mmu_TLBMissExcOffset 0 debug_jtagInstanceID 0 resetOffset 0 exceptionOffset 32 cpuID 0 cpuID_stored 0 breakOffset 32 userDefinedSettings resetSlave onchip_memory2.s1 mmu_TLBMissExcSlave exceptionSlave onchip_memory2.s1 breakSlave cpu.jtag_debug_module setting_perfCounterWidth 32 setting_interruptControllerType Internal setting_branchPredictionType Automatic setting_bhtPtrSz 8 muldiv_multiplierType EmbeddedMulFast mpu_minInstRegionSize 12 mpu_minDataRegionSize 12 mmu_uitlbNumEntries 4 mmu_udtlbNumEntries 6 mmu_tlbPtrSz 7 mmu_tlbNumWays 16 mmu_processIDNumBits 8 impl Fast icache_size 4096 icache_tagramBlockType Automatic icache_ramBlockType Automatic icache_numTCIM 0 icache_burstType None dcache_bursts false dcache_victim_buf_impl ram debug_level Level1 debug_OCIOnchipTrace _128 dcache_size 2048 dcache_tagramBlockType Automatic dcache_ramBlockType Automatic dcache_numTCDM 0 dcache_lineSize 32 setting_exportvectors false setting_ecc_present false setting_ic_ecc_present true setting_rf_ecc_present true setting_mmu_ecc_present true setting_dc_ecc_present false setting_itcm_ecc_present false setting_dtcm_ecc_present false regfile_ramBlockType Automatic ocimem_ramBlockType Automatic mmu_ramBlockType Automatic bht_ramBlockType Automatic resetAbsoluteAddr 524288 exceptionAbsoluteAddr 524320 breakAbsoluteAddr 4128 mmu_TLBMissExcAbsAddr 0 dcache_bursts_derived false dcache_size_derived 2048 dcache_lineSize_derived 32 translate_on "synthesis translate_on" translate_off "synthesis translate_off" instAddrWidth 20 dataAddrWidth 26 tightlyCoupledDataMaster0AddrWidth 1 tightlyCoupledDataMaster1AddrWidth 1 tightlyCoupledDataMaster2AddrWidth 1 tightlyCoupledDataMaster3AddrWidth 1 tightlyCoupledInstructionMaster0AddrWidth 1 tightlyCoupledInstructionMaster1AddrWidth 1 tightlyCoupledInstructionMaster2AddrWidth 1 tightlyCoupledInstructionMaster3AddrWidth 1 instSlaveMapParam <address-map><slave name='cpu.jtag_debug_module' start='0x1000' end='0x1800' /><slave name='onchip_memory2.s1' start='0x80000' end='0xA7100' /></address-map> dataSlaveMapParam <address-map><slave name='timer_stamp.s1' start='0x0' end='0x20' /><slave name='uart.s1' start='0x20' end='0x40' /><slave name='audio.avalon_slave' start='0x40' end='0x60' /><slave name='jtag_uart.avalon_jtag_slave' start='0x60' end='0x68' /><slave name='cpu.jtag_debug_module' start='0x1000' end='0x1800' /><slave name='alt_vip_cti_0.control' start='0x10080' end='0x100C0' /><slave name='alt_vip_mix_0.control' start='0x10100' end='0x10200' /><slave name='onchip_memory2.s1' start='0x80000' end='0xA7100' /><slave name='spi_0.spi_control_port' start='0x1000000' end='0x1000020' /><slave name='timer.s1' start='0x3000000' end='0x3000020' /><slave name='td_reset_n.s1' start='0x3000020' end='0x3000030' /><slave name='td_status.s1' start='0x3000030' end='0x3000040' /><slave name='i2c_sda.s1' start='0x3000040' end='0x3000050' /><slave name='i2c_scl.s1' start='0x3000050' end='0x3000060' /><slave name='sysid.control_slave' start='0x3000060' end='0x3000068' /></address-map> clockFrequency 130000000 deviceFamilyName CYCLONEV internalIrqMaskSystemInfo 403 customInstSlavesSystemInfo <info/> deviceFeaturesSystemInfo ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 tightlyCoupledDataMaster0MapParam tightlyCoupledDataMaster1MapParam tightlyCoupledDataMaster2MapParam tightlyCoupledDataMaster3MapParam tightlyCoupledInstructionMaster0MapParam tightlyCoupledInstructionMaster1MapParam tightlyCoupledInstructionMaster2MapParam tightlyCoupledInstructionMaster3MapParam deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIG_ENDIAN 0 BREAK_ADDR 0x00001020 CPU_FREQ 130000000u CPU_ID_SIZE 1 CPU_ID_VALUE 0x00000000 CPU_IMPLEMENTATION "fast" DATA_ADDR_WIDTH 26 DCACHE_LINE_SIZE 32 DCACHE_LINE_SIZE_LOG2 5 DCACHE_SIZE 2048 EXCEPTION_ADDR 0x00080020 FLUSHDA_SUPPORTED HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 HAS_DEBUG_CORE 1 HAS_DEBUG_STUB HAS_JMPI_INSTRUCTION ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 4096 INITDA_SUPPORTED INST_ADDR_WIDTH 20 NUM_OF_SHADOW_REG_SETS 0 RESET_ADDR 0x00080000

---

sysid

altera_avalon_sysid_qsys v13.1

Parameters id 0 timestamp 1400224820 AUTO_CLK_CLOCK_RATE 10000000 AUTO_DEVICE_FAMILY CYCLONEV deviceFamily Cyclone V generateLegacySim false

  

Software Assignments ID 0 TIMESTAMP 1400224820

---

alt_vip_cl_scl_0

alt_vip_cl_scl v13.1

Parameters FAMILY CYCLONEV SYMBOLS_IN_SEQ 1 SYMBOLS_IN_PAR 3 BITS_PER_SYMBOL 8 EXTRA_PIPELINING 0 IS_422 0 NO_BLANKING 1 MAX_IN_WIDTH 640 MAX_IN_HEIGHT 480 MAX_OUT_WIDTH 270 MAX_OUT_HEIGHT 200 RUNTIME_CONTROL 0 ALWAYS_DOWNSCALE 1 ALGORITHM_NAME POLYPHASE DEFAULT_EDGE_THRESH 7 DEFAULT_UPPER_BLUR 15 DEFAULT_LOWER_BLUR 0 ENABLE_FIR 0 ARE_IDENTICAL 1 V_TAPS 8 V_PHASES 16 H_TAPS 8 H_PHASES 16 V_SIGNED 1 V_INTEGER_BITS 1 V_FRACTION_BITS 7 H_SIGNED 1 H_INTEGER_BITS 1 H_FRACTION_BITS 7 PRESERVE_BITS 0 LOAD_AT_RUNTIME 0 V_BANKS 1 V_SYMMETRIC 0 V_FUNCTION LANCZOS_2 V_COEFF_FILE <enter file name (including full path)> H_BANKS 1 H_SYMMETRIC 0 H_FUNCTION LANCZOS_2 H_COEFF_FILE <enter file name (including full path)> IS_420 0 AUTO_MAIN_CLOCK_CLOCK_RATE 130000000 AUTO_MAIN_CLOCK_CLOCK_DOMAIN 8 AUTO_MAIN_CLOCK_RESET_DOMAIN 8 AUTO_DEVICE 5CSEMA5F31C6 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

pll_sys

altera_pll v13.1

Parameters debug_print_output false debug_use_rbc_taf_method false device_family CYCLONEV device 5CSEMA5F31C6 gui_device_speed_grade 8 gui_pll_mode Integer-N PLL fractional_vco_multiplier false gui_reference_clock_frequency 50.0 reference_clock_frequency 50.0 MHz gui_channel_spacing 0.0 gui_operation_mode normal gui_feedback_clock Global Clock gui_fractional_cout 32 pll_fractional_cout 32 gui_dsm_out_sel 1st_order pll_dsm_out_sel 1st_order operation_mode normal gui_use_locked true gui_en_adv_params false gui_number_of_clocks 5 number_of_clocks 5 number_of_cascade_counters 0 gui_multiply_factor 1 gui_frac_multiply_factor 1 gui_divide_factor_n 1 gui_cascade_counter0 false gui_output_clock_frequency0 130.0 gui_divide_factor_c0 1 gui_actual_multiply_factor0 52 gui_actual_frac_multiply_factor0 1 gui_actual_divide_factor0 20 gui_actual_output_clock_frequency0 0 MHz gui_ps_units0 ps gui_phase_shift0 0 gui_phase_shift_deg0 0.0 gui_actual_phase_shift0 0 gui_duty_cycle0 50 gui_cascade_counter1 false gui_output_clock_frequency1 130.0 gui_divide_factor_c1 1 gui_actual_multiply_factor1 52 gui_actual_frac_multiply_factor1 1 gui_actual_divide_factor1 20 gui_actual_output_clock_frequency1 0 MHz gui_ps_units1 degrees gui_phase_shift1 7500 gui_phase_shift_deg1 -90.0 gui_actual_phase_shift1 0 gui_duty_cycle1 50 gui_cascade_counter2 false gui_output_clock_frequency2 10.0 gui_divide_factor_c2 1 gui_actual_multiply_factor2 52 gui_actual_frac_multiply_factor2 1 gui_actual_divide_factor2 260 gui_actual_output_clock_frequency2 0 MHz gui_ps_units2 ps gui_phase_shift2 0 gui_phase_shift_deg2 0.0 gui_actual_phase_shift2 0 gui_duty_cycle2 50 gui_cascade_counter3 false gui_output_clock_frequency3 65.0 gui_divide_factor_c3 1 gui_actual_multiply_factor3 52 gui_actual_frac_multiply_factor3 1 gui_actual_divide_factor3 40 gui_actual_output_clock_frequency3 0 MHz gui_ps_units3 ps gui_phase_shift3 0 gui_phase_shift_deg3 0.0 gui_actual_phase_shift3 0 gui_duty_cycle3 50 gui_cascade_counter4 false gui_output_clock_frequency4 40.0 gui_divide_factor_c4 1 gui_actual_multiply_factor4 52 gui_actual_frac_multiply_factor4 1 gui_actual_divide_factor4 65 gui_actual_output_clock_frequency4 0 MHz gui_ps_units4 ps gui_phase_shift4 0 gui_phase_shift_deg4 0.0 gui_actual_phase_shift4 0 gui_duty_cycle4 50 gui_cascade_counter5 false gui_output_clock_frequency5 100.0 gui_divide_factor_c5 1 gui_actual_multiply_factor5 1 gui_actual_frac_multiply_factor5 1 gui_actual_divide_factor5 1 gui_actual_output_clock_frequency5 0 MHz gui_ps_units5 ps gui_phase_shift5 0 gui_phase_shift_deg5 0.0 gui_actual_phase_shift5 0 gui_duty_cycle5 50 gui_cascade_counter6 false gui_output_clock_frequency6 100.0 gui_divide_factor_c6 1 gui_actual_multiply_factor6 1 gui_actual_frac_multiply_factor6 1 gui_actual_divide_factor6 1 gui_actual_output_clock_frequency6 0 MHz gui_ps_units6 ps gui_phase_shift6 0 gui_phase_shift_deg6 0.0 gui_actual_phase_shift6 0 gui_duty_cycle6 50 gui_cascade_counter7 false gui_output_clock_frequency7 100.0 gui_divide_factor_c7 1 gui_actual_multiply_factor7 1 gui_actual_frac_multiply_factor7 1 gui_actual_divide_factor7 1 gui_actual_output_clock_frequency7 0 MHz gui_ps_units7 ps gui_phase_shift7 0 gui_phase_shift_deg7 0.0 gui_actual_phase_shift7 0 gui_duty_cycle7 50 gui_cascade_counter8 false gui_output_clock_frequency8 100.0 gui_divide_factor_c8 1 gui_actual_multiply_factor8 1 gui_actual_frac_multiply_factor8 1 gui_actual_divide_factor8 1 gui_actual_output_clock_frequency8 0 MHz gui_ps_units8 ps gui_phase_shift8 0 gui_phase_shift_deg8 0.0 gui_actual_phase_shift8 0 gui_duty_cycle8 50 gui_cascade_counter9 false gui_output_clock_frequency9 100.0 gui_divide_factor_c9 1 gui_actual_multiply_factor9 1 gui_actual_frac_multiply_factor9 1 gui_actual_divide_factor9 1 gui_actual_output_clock_frequency9 0 MHz gui_ps_units9 ps gui_phase_shift9 0 gui_phase_shift_deg9 0.0 gui_actual_phase_shift9 0 gui_duty_cycle9 50 gui_cascade_counter10 false gui_output_clock_frequency10 100.0 gui_divide_factor_c10 1 gui_actual_multiply_factor10 1 gui_actual_frac_multiply_factor10 1 gui_actual_divide_factor10 1 gui_actual_output_clock_frequency10 0 MHz gui_ps_units10 ps gui_phase_shift10 0 gui_phase_shift_deg10 0.0 gui_actual_phase_shift10 0 gui_duty_cycle10 50 gui_cascade_counter11 false gui_output_clock_frequency11 100.0 gui_divide_factor_c11 1 gui_actual_multiply_factor11 1 gui_actual_frac_multiply_factor11 1 gui_actual_divide_factor11 1 gui_actual_output_clock_frequency11 0 MHz gui_ps_units11 ps gui_phase_shift11 0 gui_phase_shift_deg11 0.0 gui_actual_phase_shift11 0 gui_duty_cycle11 50 gui_cascade_counter12 false gui_output_clock_frequency12 100.0 gui_divide_factor_c12 1 gui_actual_multiply_factor12 1 gui_actual_frac_multiply_factor12 1 gui_actual_divide_factor12 1 gui_actual_output_clock_frequency12 0 MHz gui_ps_units12 ps gui_phase_shift12 0 gui_phase_shift_deg12 0.0 gui_actual_phase_shift12 0 gui_duty_cycle12 50 gui_cascade_counter13 false gui_output_clock_frequency13 100.0 gui_divide_factor_c13 1 gui_actual_multiply_factor13 1 gui_actual_frac_multiply_factor13 1 gui_actual_divide_factor13 1 gui_actual_output_clock_frequency13 0 MHz gui_ps_units13 ps gui_phase_shift13 0 gui_phase_shift_deg13 0.0 gui_actual_phase_shift13 0 gui_duty_cycle13 50 gui_cascade_counter14 false gui_output_clock_frequency14 100.0 gui_divide_factor_c14 1 gui_actual_multiply_factor14 1 gui_actual_frac_multiply_factor14 1 gui_actual_divide_factor14 1 gui_actual_output_clock_frequency14 0 MHz gui_ps_units14 ps gui_phase_shift14 0 gui_phase_shift_deg14 0.0 gui_actual_phase_shift14 0 gui_duty_cycle14 50 gui_cascade_counter15 false gui_output_clock_frequency15 100.0 gui_divide_factor_c15 1 gui_actual_multiply_factor15 1 gui_actual_frac_multiply_factor15 1 gui_actual_divide_factor15 1 gui_actual_output_clock_frequency15 0 MHz gui_ps_units15 ps gui_phase_shift15 0 gui_phase_shift_deg15 0.0 gui_actual_phase_shift15 0 gui_duty_cycle15 50 gui_cascade_counter16 false gui_output_clock_frequency16 100.0 gui_divide_factor_c16 1 gui_actual_multiply_factor16 1 gui_actual_frac_multiply_factor16 1 gui_actual_divide_factor16 1 gui_actual_output_clock_frequency16 0 MHz gui_ps_units16 ps gui_phase_shift16 0 gui_phase_shift_deg16 0.0 gui_actual_phase_shift16 0 gui_duty_cycle16 50 gui_cascade_counter17 false gui_output_clock_frequency17 100.0 gui_divide_factor_c17 1 gui_actual_multiply_factor17 1 gui_actual_frac_multiply_factor17 1 gui_actual_divide_factor17 1 gui_actual_output_clock_frequency17 0 MHz gui_ps_units17 ps gui_phase_shift17 0 gui_phase_shift_deg17 0.0 gui_actual_phase_shift17 0 gui_duty_cycle17 50 output_clock_frequency0 130.000000 MHz phase_shift0 0 ps duty_cycle0 50 output_clock_frequency1 130.000000 MHz phase_shift1 5769 ps duty_cycle1 50 output_clock_frequency2 10.000000 MHz phase_shift2 0 ps duty_cycle2 50 output_clock_frequency3 65.000000 MHz phase_shift3 0 ps duty_cycle3 50 output_clock_frequency4 40.000000 MHz phase_shift4 0 ps duty_cycle4 50 output_clock_frequency5 0 MHz phase_shift5 0 ps duty_cycle5 50 output_clock_frequency6 0 MHz phase_shift6 0 ps duty_cycle6 50 output_clock_frequency7 0 MHz phase_shift7 0 ps duty_cycle7 50 output_clock_frequency8 0 MHz phase_shift8 0 ps duty_cycle8 50 output_clock_frequency9 0 MHz phase_shift9 0 ps duty_cycle9 50 output_clock_frequency10 0 MHz phase_shift10 0 ps duty_cycle10 50 output_clock_frequency11 0 MHz phase_shift11 0 ps duty_cycle11 50 output_clock_frequency12 0 MHz phase_shift12 0 ps duty_cycle12 50 output_clock_frequency13 0 MHz phase_shift13 0 ps duty_cycle13 50 output_clock_frequency14 0 MHz phase_shift14 0 ps duty_cycle14 50 output_clock_frequency15 0 MHz phase_shift15 0 ps duty_cycle15 50 output_clock_frequency16 0 MHz phase_shift16 0 ps duty_cycle16 50 output_clock_frequency17 0 MHz phase_shift17 0 ps duty_cycle17 50 gui_pll_auto_reset Off gui_pll_bandwidth_preset Auto gui_en_reconf false gui_en_dps_ports false gui_en_phout_ports false gui_phout_division 1 gui_en_lvds_ports false pll_vcoph_div 1 pll_type General pll_subtype General m_cnt_hi_div 26 m_cnt_lo_div 26 n_cnt_hi_div 3 n_cnt_lo_div 2 m_cnt_bypass_en false n_cnt_bypass_en false m_cnt_odd_div_duty_en false n_cnt_odd_div_duty_en true c_cnt_hi_div0 2 c_cnt_lo_div0 2 c_cnt_prst0 1 c_cnt_ph_mux_prst0 0 c_cnt_in_src0 ph_mux_clk c_cnt_bypass_en0 false c_cnt_odd_div_duty_en0 false c_cnt_hi_div1 2 c_cnt_lo_div1 2 c_cnt_prst1 4 c_cnt_ph_mux_prst1 0 c_cnt_in_src1 ph_mux_clk c_cnt_bypass_en1 false c_cnt_odd_div_duty_en1 false c_cnt_hi_div2 26 c_cnt_lo_div2 26 c_cnt_prst2 1 c_cnt_ph_mux_prst2 0 c_cnt_in_src2 ph_mux_clk c_cnt_bypass_en2 false c_cnt_odd_div_duty_en2 false c_cnt_hi_div3 4 c_cnt_lo_div3 4 c_cnt_prst3 1 c_cnt_ph_mux_prst3 0 c_cnt_in_src3 ph_mux_clk c_cnt_bypass_en3 false c_cnt_odd_div_duty_en3 false c_cnt_hi_div4 7 c_cnt_lo_div4 6 c_cnt_prst4 1 c_cnt_ph_mux_prst4 0 c_cnt_in_src4 ph_mux_clk c_cnt_bypass_en4 false c_cnt_odd_div_duty_en4 true c_cnt_hi_div5 1 c_cnt_lo_div5 1 c_cnt_prst5 1 c_cnt_ph_mux_prst5 0 c_cnt_in_src5 ph_mux_clk c_cnt_bypass_en5 true c_cnt_odd_div_duty_en5 false c_cnt_hi_div6 1 c_cnt_lo_div6 1 c_cnt_prst6 1 c_cnt_ph_mux_prst6 0 c_cnt_in_src6 ph_mux_clk c_cnt_bypass_en6 true c_cnt_odd_div_duty_en6 false c_cnt_hi_div7 1 c_cnt_lo_div7 1 c_cnt_prst7 1 c_cnt_ph_mux_prst7 0 c_cnt_in_src7 ph_mux_clk c_cnt_bypass_en7 true c_cnt_odd_div_duty_en7 false c_cnt_hi_div8 1 c_cnt_lo_div8 1 c_cnt_prst8 1 c_cnt_ph_mux_prst8 0 c_cnt_in_src8 ph_mux_clk c_cnt_bypass_en8 true c_cnt_odd_div_duty_en8 false c_cnt_hi_div9 1 c_cnt_lo_div9 1 c_cnt_prst9 1 c_cnt_ph_mux_prst9 0 c_cnt_in_src9 ph_mux_clk c_cnt_bypass_en9 true c_cnt_odd_div_duty_en9 false c_cnt_hi_div10 1 c_cnt_lo_div10 1 c_cnt_prst10 1 c_cnt_ph_mux_prst10 0 c_cnt_in_src10 ph_mux_clk c_cnt_bypass_en10 true c_cnt_odd_div_duty_en10 false c_cnt_hi_div11 1 c_cnt_lo_div11 1 c_cnt_prst11 1 c_cnt_ph_mux_prst11 0 c_cnt_in_src11 ph_mux_clk c_cnt_bypass_en11 true c_cnt_odd_div_duty_en11 false c_cnt_hi_div12 1 c_cnt_lo_div12 1 c_cnt_prst12 1 c_cnt_ph_mux_prst12 0 c_cnt_in_src12 ph_mux_clk c_cnt_bypass_en12 true c_cnt_odd_div_duty_en12 false c_cnt_hi_div13 1 c_cnt_lo_div13 1 c_cnt_prst13 1 c_cnt_ph_mux_prst13 0 c_cnt_in_src13 ph_mux_clk c_cnt_bypass_en13 true c_cnt_odd_div_duty_en13 false c_cnt_hi_div14 1 c_cnt_lo_div14 1 c_cnt_prst14 1 c_cnt_ph_mux_prst14 0 c_cnt_in_src14 ph_mux_clk c_cnt_bypass_en14 true c_cnt_odd_div_duty_en14 false c_cnt_hi_div15 1 c_cnt_lo_div15 1 c_cnt_prst15 1 c_cnt_ph_mux_prst15 0 c_cnt_in_src15 ph_mux_clk c_cnt_bypass_en15 true c_cnt_odd_div_duty_en15 false c_cnt_hi_div16 1 c_cnt_lo_div16 1 c_cnt_prst16 1 c_cnt_ph_mux_prst16 0 c_cnt_in_src16 ph_mux_clk c_cnt_bypass_en16 true c_cnt_odd_div_duty_en16 false c_cnt_hi_div17 1 c_cnt_lo_div17 1 c_cnt_prst17 1 c_cnt_ph_mux_prst17 0 c_cnt_in_src17 ph_mux_clk c_cnt_bypass_en17 true c_cnt_odd_div_duty_en17 false pll_vco_div 2 pll_cp_current 20 pll_bwctrl 10000 pll_output_clk_frequency 520.0 MHz pll_fractional_division 1 mimic_fbclk_type gclk pll_fbclk_mux_1 glb pll_fbclk_mux_2 fb_1 pll_m_cnt_in_src ph_mux_clk pll_slf_rst false gui_parameter_list M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,C-Counter-4 Hi Divide,C-Counter-4 Low Divide,C-Counter-4 Coarse Phase Shift,C-Counter-4 VCO Phase Tap,C-Counter-4 Input Source,C-Counter-4 Bypass Enable,C-Counter-4 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset gui_parameter_values 26,26,3,2,false,false,false,true,2,2,1,0,ph_mux_clk,false,false,2,2,4,0,ph_mux_clk,false,false,26,26,1,0,ph_mux_clk,false,false,4,4,1,0,ph_mux_clk,false,false,7,6,1,0,ph_mux_clk,false,true,2,20,10000,520.0 MHz,1,gclk,glb,fb_1,ph_mux_clk,false gui_mif_generate false gui_enable_mif_dps false gui_dps_cntr C0 gui_dps_num 1 gui_dps_dir Positive gui_refclk_switch false gui_refclk1_frequency 100.0 gui_switchover_mode Automatic Switchover gui_switchover_delay 0 gui_active_clk false gui_clk_bad false refclk1_frequency 100.0 MHz pll_clk_loss_sw_en false pll_manu_clk_sw_en false pll_auto_clk_sw_en false pll_clkin_1_src clk_0 pll_clk_sw_dly 0 gui_enable_cascade_out false gui_cascade_outclk_index 0 gui_enable_cascade_in false pll_clkin_0_src clk_0 gui_pll_cascading_mode Create an adjpllin signal to connect with an upstream PLL AUTO_REFCLK_CLOCK_RATE 50000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

seg7

SEG7_IF v1.0

Parameters SEG7_NUM 6 ADDR_WIDTH 3 DEFAULT_ACTIVE 1 LOW_ACTIVE 1 AUTO_CLOCK_SINK_CLOCK_RATE 10000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

sw

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true direction Input edgeType ANY generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 10 clockRate 10000000 derived_has_tri false derived_has_out false derived_has_in true derived_do_test_bench_wiring false derived_capture true derived_edge_type ANY derived_irq_type EDGE derived_has_irq true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 1 DATA_WIDTH 10 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE ANY FREQ 10000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE EDGE RESET_VALUE 0

---

key

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true direction Input edgeType ANY generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 4 clockRate 10000000 derived_has_tri false derived_has_out false derived_has_in true derived_do_test_bench_wiring false derived_capture true derived_edge_type ANY derived_irq_type EDGE derived_has_irq true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 1 DATA_WIDTH 4 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE ANY FREQ 10000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE EDGE RESET_VALUE 0

---

ledr

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 10 clockRate 10000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 10 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 10000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

spi_0

altera_avalon_spi v13.1

Parameters clockPhase 0 clockPolarity 1 dataWidth 16 disableAvalonFlowControl false insertDelayBetweenSlaveSelectAndSClk false insertSync false lsbOrderedFirst false masterSPI true numberOfSlaves 1 syncRegDepth 2 targetClockRate 20000000 targetSlaveSelectToSClkDelay 0.0 avalonSpec 2.0 inputClockRate 40000000 actualClockRate 2.0E7 actualSlaveSelectToSClkDelay 0.0 legacySignalsAllow false slaveDataBusWidth 16 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CLOCKMULT 1 CLOCKPHASE 0 CLOCKPOLARITY 1 CLOCKUNITS "Hz" DATABITS 16 DATAWIDTH 16 DELAYMULT "1.0E-9" DELAYUNITS "ns" EXTRADELAY 0 INSERT_SYNC 0 ISMASTER 1 LSBFIRST 0 NUMSLAVES 1 PREFIX "spi_" SYNC_REG_DEPTH 2 TARGETCLOCK 20000000u TARGETSSDELAY "0.0"

---

audio

AUDIO_IF v1.0

Parameters AUTO_CLOCK_SINK_CLOCK_RATE 18432000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

pll_audio

altera_pll v13.1

Parameters debug_print_output false debug_use_rbc_taf_method false device_family CYCLONEV device 5CSEMA5F31C6 gui_device_speed_grade 2 gui_pll_mode Fractional-N PLL fractional_vco_multiplier true gui_reference_clock_frequency 50.0 reference_clock_frequency 50.0 MHz gui_channel_spacing 0.0 gui_operation_mode normal gui_feedback_clock Global Clock gui_fractional_cout 32 pll_fractional_cout 32 gui_dsm_out_sel 1st_order pll_dsm_out_sel 1st_order operation_mode normal gui_use_locked true gui_en_adv_params false gui_number_of_clocks 1 number_of_clocks 1 number_of_cascade_counters 0 gui_multiply_factor 1 gui_frac_multiply_factor 1 gui_divide_factor_n 1 gui_cascade_counter0 false gui_output_clock_frequency0 18.432 gui_divide_factor_c0 1 gui_actual_multiply_factor0 8 gui_actual_frac_multiply_factor0 472790000 gui_actual_divide_factor0 22 gui_actual_output_clock_frequency0 0 MHz gui_ps_units0 ps gui_phase_shift0 0 gui_phase_shift_deg0 0.0 gui_actual_phase_shift0 0 gui_duty_cycle0 50 gui_cascade_counter1 false gui_output_clock_frequency1 100.0 gui_divide_factor_c1 1 gui_actual_multiply_factor1 1 gui_actual_frac_multiply_factor1 1 gui_actual_divide_factor1 1 gui_actual_output_clock_frequency1 0 MHz gui_ps_units1 ps gui_phase_shift1 0 gui_phase_shift_deg1 0.0 gui_actual_phase_shift1 0 gui_duty_cycle1 50 gui_cascade_counter2 false gui_output_clock_frequency2 100.0 gui_divide_factor_c2 1 gui_actual_multiply_factor2 1 gui_actual_frac_multiply_factor2 1 gui_actual_divide_factor2 1 gui_actual_output_clock_frequency2 0 MHz gui_ps_units2 ps gui_phase_shift2 0 gui_phase_shift_deg2 0.0 gui_actual_phase_shift2 0 gui_duty_cycle2 50 gui_cascade_counter3 false gui_output_clock_frequency3 100.0 gui_divide_factor_c3 1 gui_actual_multiply_factor3 1 gui_actual_frac_multiply_factor3 1 gui_actual_divide_factor3 1 gui_actual_output_clock_frequency3 0 MHz gui_ps_units3 ps gui_phase_shift3 0 gui_phase_shift_deg3 0.0 gui_actual_phase_shift3 0 gui_duty_cycle3 50 gui_cascade_counter4 false gui_output_clock_frequency4 100.0 gui_divide_factor_c4 1 gui_actual_multiply_factor4 1 gui_actual_frac_multiply_factor4 1 gui_actual_divide_factor4 1 gui_actual_output_clock_frequency4 0 MHz gui_ps_units4 ps gui_phase_shift4 0 gui_phase_shift_deg4 0.0 gui_actual_phase_shift4 0 gui_duty_cycle4 50 gui_cascade_counter5 false gui_output_clock_frequency5 100.0 gui_divide_factor_c5 1 gui_actual_multiply_factor5 1 gui_actual_frac_multiply_factor5 1 gui_actual_divide_factor5 1 gui_actual_output_clock_frequency5 0 MHz gui_ps_units5 ps gui_phase_shift5 0 gui_phase_shift_deg5 0.0 gui_actual_phase_shift5 0 gui_duty_cycle5 50 gui_cascade_counter6 false gui_output_clock_frequency6 100.0 gui_divide_factor_c6 1 gui_actual_multiply_factor6 1 gui_actual_frac_multiply_factor6 1 gui_actual_divide_factor6 1 gui_actual_output_clock_frequency6 0 MHz gui_ps_units6 ps gui_phase_shift6 0 gui_phase_shift_deg6 0.0 gui_actual_phase_shift6 0 gui_duty_cycle6 50 gui_cascade_counter7 false gui_output_clock_frequency7 100.0 gui_divide_factor_c7 1 gui_actual_multiply_factor7 1 gui_actual_frac_multiply_factor7 1 gui_actual_divide_factor7 1 gui_actual_output_clock_frequency7 0 MHz gui_ps_units7 ps gui_phase_shift7 0 gui_phase_shift_deg7 0.0 gui_actual_phase_shift7 0 gui_duty_cycle7 50 gui_cascade_counter8 false gui_output_clock_frequency8 100.0 gui_divide_factor_c8 1 gui_actual_multiply_factor8 1 gui_actual_frac_multiply_factor8 1 gui_actual_divide_factor8 1 gui_actual_output_clock_frequency8 0 MHz gui_ps_units8 ps gui_phase_shift8 0 gui_phase_shift_deg8 0.0 gui_actual_phase_shift8 0 gui_duty_cycle8 50 gui_cascade_counter9 false gui_output_clock_frequency9 100.0 gui_divide_factor_c9 1 gui_actual_multiply_factor9 1 gui_actual_frac_multiply_factor9 1 gui_actual_divide_factor9 1 gui_actual_output_clock_frequency9 0 MHz gui_ps_units9 ps gui_phase_shift9 0 gui_phase_shift_deg9 0.0 gui_actual_phase_shift9 0 gui_duty_cycle9 50 gui_cascade_counter10 false gui_output_clock_frequency10 100.0 gui_divide_factor_c10 1 gui_actual_multiply_factor10 1 gui_actual_frac_multiply_factor10 1 gui_actual_divide_factor10 1 gui_actual_output_clock_frequency10 0 MHz gui_ps_units10 ps gui_phase_shift10 0 gui_phase_shift_deg10 0.0 gui_actual_phase_shift10 0 gui_duty_cycle10 50 gui_cascade_counter11 false gui_output_clock_frequency11 100.0 gui_divide_factor_c11 1 gui_actual_multiply_factor11 1 gui_actual_frac_multiply_factor11 1 gui_actual_divide_factor11 1 gui_actual_output_clock_frequency11 0 MHz gui_ps_units11 ps gui_phase_shift11 0 gui_phase_shift_deg11 0.0 gui_actual_phase_shift11 0 gui_duty_cycle11 50 gui_cascade_counter12 false gui_output_clock_frequency12 100.0 gui_divide_factor_c12 1 gui_actual_multiply_factor12 1 gui_actual_frac_multiply_factor12 1 gui_actual_divide_factor12 1 gui_actual_output_clock_frequency12 0 MHz gui_ps_units12 ps gui_phase_shift12 0 gui_phase_shift_deg12 0.0 gui_actual_phase_shift12 0 gui_duty_cycle12 50 gui_cascade_counter13 false gui_output_clock_frequency13 100.0 gui_divide_factor_c13 1 gui_actual_multiply_factor13 1 gui_actual_frac_multiply_factor13 1 gui_actual_divide_factor13 1 gui_actual_output_clock_frequency13 0 MHz gui_ps_units13 ps gui_phase_shift13 0 gui_phase_shift_deg13 0.0 gui_actual_phase_shift13 0 gui_duty_cycle13 50 gui_cascade_counter14 false gui_output_clock_frequency14 100.0 gui_divide_factor_c14 1 gui_actual_multiply_factor14 1 gui_actual_frac_multiply_factor14 1 gui_actual_divide_factor14 1 gui_actual_output_clock_frequency14 0 MHz gui_ps_units14 ps gui_phase_shift14 0 gui_phase_shift_deg14 0.0 gui_actual_phase_shift14 0 gui_duty_cycle14 50 gui_cascade_counter15 false gui_output_clock_frequency15 100.0 gui_divide_factor_c15 1 gui_actual_multiply_factor15 1 gui_actual_frac_multiply_factor15 1 gui_actual_divide_factor15 1 gui_actual_output_clock_frequency15 0 MHz gui_ps_units15 ps gui_phase_shift15 0 gui_phase_shift_deg15 0.0 gui_actual_phase_shift15 0 gui_duty_cycle15 50 gui_cascade_counter16 false gui_output_clock_frequency16 100.0 gui_divide_factor_c16 1 gui_actual_multiply_factor16 1 gui_actual_frac_multiply_factor16 1 gui_actual_divide_factor16 1 gui_actual_output_clock_frequency16 0 MHz gui_ps_units16 ps gui_phase_shift16 0 gui_phase_shift_deg16 0.0 gui_actual_phase_shift16 0 gui_duty_cycle16 50 gui_cascade_counter17 false gui_output_clock_frequency17 100.0 gui_divide_factor_c17 1 gui_actual_multiply_factor17 1 gui_actual_frac_multiply_factor17 1 gui_actual_divide_factor17 1 gui_actual_output_clock_frequency17 0 MHz gui_ps_units17 ps gui_phase_shift17 0 gui_phase_shift_deg17 0.0 gui_actual_phase_shift17 0 gui_duty_cycle17 50 output_clock_frequency0 18.432000 MHz phase_shift0 0 ps duty_cycle0 50 output_clock_frequency1 0 MHz phase_shift1 0 ps duty_cycle1 50 output_clock_frequency2 0 MHz phase_shift2 0 ps duty_cycle2 50 output_clock_frequency3 0 MHz phase_shift3 0 ps duty_cycle3 50 output_clock_frequency4 0 MHz phase_shift4 0 ps duty_cycle4 50 output_clock_frequency5 0 MHz phase_shift5 0 ps duty_cycle5 50 output_clock_frequency6 0 MHz phase_shift6 0 ps duty_cycle6 50 output_clock_frequency7 0 MHz phase_shift7 0 ps duty_cycle7 50 output_clock_frequency8 0 MHz phase_shift8 0 ps duty_cycle8 50 output_clock_frequency9 0 MHz phase_shift9 0 ps duty_cycle9 50 output_clock_frequency10 0 MHz phase_shift10 0 ps duty_cycle10 50 output_clock_frequency11 0 MHz phase_shift11 0 ps duty_cycle11 50 output_clock_frequency12 0 MHz phase_shift12 0 ps duty_cycle12 50 output_clock_frequency13 0 MHz phase_shift13 0 ps duty_cycle13 50 output_clock_frequency14 0 MHz phase_shift14 0 ps duty_cycle14 50 output_clock_frequency15 0 MHz phase_shift15 0 ps duty_cycle15 50 output_clock_frequency16 0 MHz phase_shift16 0 ps duty_cycle16 50 output_clock_frequency17 0 MHz phase_shift17 0 ps duty_cycle17 50 gui_pll_auto_reset Off gui_pll_bandwidth_preset Auto gui_en_reconf false gui_en_dps_ports false gui_en_phout_ports false gui_phout_division 1 gui_en_lvds_ports false pll_vcoph_div 1 pll_type General pll_subtype General m_cnt_hi_div 4 m_cnt_lo_div 4 n_cnt_hi_div 256 n_cnt_lo_div 256 m_cnt_bypass_en false n_cnt_bypass_en true m_cnt_odd_div_duty_en false n_cnt_odd_div_duty_en false c_cnt_hi_div0 11 c_cnt_lo_div0 11 c_cnt_prst0 1 c_cnt_ph_mux_prst0 0 c_cnt_in_src0 ph_mux_clk c_cnt_bypass_en0 false c_cnt_odd_div_duty_en0 false c_cnt_hi_div1 1 c_cnt_lo_div1 1 c_cnt_prst1 1 c_cnt_ph_mux_prst1 0 c_cnt_in_src1 ph_mux_clk c_cnt_bypass_en1 true c_cnt_odd_div_duty_en1 false c_cnt_hi_div2 1 c_cnt_lo_div2 1 c_cnt_prst2 1 c_cnt_ph_mux_prst2 0 c_cnt_in_src2 ph_mux_clk c_cnt_bypass_en2 true c_cnt_odd_div_duty_en2 false c_cnt_hi_div3 1 c_cnt_lo_div3 1 c_cnt_prst3 1 c_cnt_ph_mux_prst3 0 c_cnt_in_src3 ph_mux_clk c_cnt_bypass_en3 true c_cnt_odd_div_duty_en3 false c_cnt_hi_div4 1 c_cnt_lo_div4 1 c_cnt_prst4 1 c_cnt_ph_mux_prst4 0 c_cnt_in_src4 ph_mux_clk c_cnt_bypass_en4 true c_cnt_odd_div_duty_en4 false c_cnt_hi_div5 1 c_cnt_lo_div5 1 c_cnt_prst5 1 c_cnt_ph_mux_prst5 0 c_cnt_in_src5 ph_mux_clk c_cnt_bypass_en5 true c_cnt_odd_div_duty_en5 false c_cnt_hi_div6 1 c_cnt_lo_div6 1 c_cnt_prst6 1 c_cnt_ph_mux_prst6 0 c_cnt_in_src6 ph_mux_clk c_cnt_bypass_en6 true c_cnt_odd_div_duty_en6 false c_cnt_hi_div7 1 c_cnt_lo_div7 1 c_cnt_prst7 1 c_cnt_ph_mux_prst7 0 c_cnt_in_src7 ph_mux_clk c_cnt_bypass_en7 true c_cnt_odd_div_duty_en7 false c_cnt_hi_div8 1 c_cnt_lo_div8 1 c_cnt_prst8 1 c_cnt_ph_mux_prst8 0 c_cnt_in_src8 ph_mux_clk c_cnt_bypass_en8 true c_cnt_odd_div_duty_en8 false c_cnt_hi_div9 1 c_cnt_lo_div9 1 c_cnt_prst9 1 c_cnt_ph_mux_prst9 0 c_cnt_in_src9 ph_mux_clk c_cnt_bypass_en9 true c_cnt_odd_div_duty_en9 false c_cnt_hi_div10 1 c_cnt_lo_div10 1 c_cnt_prst10 1 c_cnt_ph_mux_prst10 0 c_cnt_in_src10 ph_mux_clk c_cnt_bypass_en10 true c_cnt_odd_div_duty_en10 false c_cnt_hi_div11 1 c_cnt_lo_div11 1 c_cnt_prst11 1 c_cnt_ph_mux_prst11 0 c_cnt_in_src11 ph_mux_clk c_cnt_bypass_en11 true c_cnt_odd_div_duty_en11 false c_cnt_hi_div12 1 c_cnt_lo_div12 1 c_cnt_prst12 1 c_cnt_ph_mux_prst12 0 c_cnt_in_src12 ph_mux_clk c_cnt_bypass_en12 true c_cnt_odd_div_duty_en12 false c_cnt_hi_div13 1 c_cnt_lo_div13 1 c_cnt_prst13 1 c_cnt_ph_mux_prst13 0 c_cnt_in_src13 ph_mux_clk c_cnt_bypass_en13 true c_cnt_odd_div_duty_en13 false c_cnt_hi_div14 1 c_cnt_lo_div14 1 c_cnt_prst14 1 c_cnt_ph_mux_prst14 0 c_cnt_in_src14 ph_mux_clk c_cnt_bypass_en14 true c_cnt_odd_div_duty_en14 false c_cnt_hi_div15 1 c_cnt_lo_div15 1 c_cnt_prst15 1 c_cnt_ph_mux_prst15 0 c_cnt_in_src15 ph_mux_clk c_cnt_bypass_en15 true c_cnt_odd_div_duty_en15 false c_cnt_hi_div16 1 c_cnt_lo_div16 1 c_cnt_prst16 1 c_cnt_ph_mux_prst16 0 c_cnt_in_src16 ph_mux_clk c_cnt_bypass_en16 true c_cnt_odd_div_duty_en16 false c_cnt_hi_div17 1 c_cnt_lo_div17 1 c_cnt_prst17 1 c_cnt_ph_mux_prst17 0 c_cnt_in_src17 ph_mux_clk c_cnt_bypass_en17 true c_cnt_odd_div_duty_en17 false pll_vco_div 2 pll_cp_current 20 pll_bwctrl 4000 pll_output_clk_frequency 405.504 MHz pll_fractional_division 472790000 mimic_fbclk_type gclk pll_fbclk_mux_1 glb pll_fbclk_mux_2 fb_1 pll_m_cnt_in_src ph_mux_clk pll_slf_rst false gui_parameter_list M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset gui_parameter_values 4,4,256,256,false,true,false,false,11,11,1,0,ph_mux_clk,false,false,2,20,4000,405.504 MHz,472790000,gclk,glb,fb_1,ph_mux_clk,false gui_mif_generate false gui_enable_mif_dps false gui_dps_cntr C0 gui_dps_num 1 gui_dps_dir Positive gui_refclk_switch false gui_refclk1_frequency 100.0 gui_switchover_mode Automatic Switchover gui_switchover_delay 0 gui_active_clk false gui_clk_bad false refclk1_frequency 100.0 MHz pll_clk_loss_sw_en false pll_manu_clk_sw_en false pll_auto_clk_sw_en false pll_clkin_1_src clk_0 pll_clk_sw_dly 0 gui_enable_cascade_out false gui_cascade_outclk_index 0 gui_enable_cascade_in false pll_clkin_0_src clk_0 gui_pll_cascading_mode Create an adjpllin signal to connect with an upstream PLL AUTO_REFCLK_CLOCK_RATE 50000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)